The present invention relates to semiconductor memory device testing, and more particularly, to a method and apparatus for detecting an overvoltage signal applied to a memory device input pin.
Advances in manufacturing processes and device design have led to improved semiconductor memory devices. Process advances have resulted in highly integrated devices which can store a large amount of information in a small area. Design advances have improved the access speed and power consumption of semiconductor memory devices, as well as the techniques by which the characteristics of a memory device are verified and analyzed. These advances have been especially noteworthy in the area of dynamic random access memory (DRAM).
In a DRAM semiconductor device, an address signal, which is normally used for selecting a specific memory cell, is used in conjunction with control signals /RAS (row address strobe), /CAS (column address strobe), and /W (write) to control read, write, refresh, and test mode operations. However, due to the limited number of control signals that are available, new test modes such as parallel test mode have been developed.
Timing signals for a parallel test mode operation are shown in FIG. 2. (Address signals have been omitted from FIG. 2.) This timing is commonly referred to as test mode timing. By entering a parallel test mode using the timing sequence shown in FIG. 2, data from more memory cells can be accessed than during a normal read or write operation, and the time required for testing all cells of a DRAM semiconductor device is reduced accordingly. For example, if data from four memory cells is accessed during a normal read or write operation, data from sixteen or more memory cells can be accessed in a parallel test mode.
In a parallel test mode, the data from four or more memory cells is compared internally and accessed through one input/output (I/O) pin. If the data from the four or more memory cells which are being tested in parallel are the same, the output from the I/O pin is "1" (high logic level). If any of the data from the four or more memory cells are different, the output is "0" (low logic level). The output information only indicates whether all of the cells tested in parallel have the same data, but does not indicate what the state of the data is.
To provide more information from a parallel test mode operation, a new method has recently been proposed. According to this new method, a parallel test mode is entered using the timing sequence shown in FIG. 2. If the data from the parallel memory cells are all "1s", a "1" is output through the I/O pin. However, if the data in the memory cells are all "0", a "0" is output through the I/O pin. If the data in any of the memory cells are different, the I/O pin is placed in a high impedance state.
To enter this new parallel test mode, overvoltage signal is applied to a specified address pin in addition to the timing sequence illustrated in FIG. 2. Thus, an overvoltage detection circuit is necessary for sensing the overvoltage signal.
A conventional overvoltage detection circuit for placing a semiconductor memory device in a parallel test mode is shown in FIG. 1. The circuit of FIG. 1 includes three NMOS transistors 11, 13, and 15 connected in series and functioning as a diode to transfer the signal Ai to a node N1. The signal Ai is an address signal during normal operation and an overvoltage signal in test mode. An NMOS transistor 17 is connected between a supply voltage signal VINT and node N1 and functions as a resistor. PMOS transistor 19 is connected between nodes N1 and N2 to transfer the voltage signal from node N1 to node N2. An NMOS transistor 21 has a current path connected between node N2 and a ground terminal and is controlled by a signal VREF applied to its gate. Two series connected inverters 23 and 25 receive the signal from node N2 and generate the signal SVAi.
In operation, when a power supply voltage is applied to the circuit, node N1 is precharged to (VINT-Vtn), where Vtn is the threshold voltage of NMOS transistor 17. NMOS transistor 21 is turned on by the reference voltage VREF, thereby pulling the voltage of node N2 to ground. Since PMOS transistor 19 is off, nodes N1 and N2 are electrically disconnected, and the voltage of node N2 forces the signal SVAi to "0". If the voltage of signal Ai is increased to an overvoltage level, the voltage of node N1 is gradually increased through the three NMOS transistors 11, 13, and 15.
If the voltage of node N1 increases to a level greater than (VINT+Vtp), where Vtp is the threshold voltage of PMOS transistor 19, PMOS transistor 19 turns on thereby causing the voltage of node N2 to increase. If the current flowing from node N1 to N2 through PMOS transistor 19 exceeds the current flowing from node N2 to ground through NMOS transistor 21, the voltage of node N2 increases, and if the voltage at node N2 exceeds the trip point of inverter 23, the signal SVAi switches to "1".
The overvoltage level applied to the input Ai is higher than the supply voltage and is only used to place the semiconductor memory device in test mode. Thereafter, the signal Ai is used as a normal address signal.
When a normal supply voltage level of 5 V is used, an overvoltage level of 7 V is applied to Ai to place the device in test mode. However, during test and development of most semiconductor memory devices, supply voltages which are greater than the normal supply voltage are often used. When a higher supply voltage is used, the overvoltage level must be increased accordingly to cause PMOS transistor 19 to turn on. The voltage of node N1 must be greater than (VINT+Vpt) to cause PMOS transistor 19 to turn on.
When a supply voltage which is greater than 5 V is used, an overvoltage level of greater than 7 V must be applied to pin Ai to place the device in test mode. However, applying a voltage greater than 7 V to an address pin stresses the semiconductor device connected to the pin and can result in damage to the device and an accompanying loss of functionality. Moreover, if the supply voltage is varied, the overvoltage level must be varied accordingly, thereby complicating and adding inconvenience to test mode operation.